Some integrated circuits are tested for reliability by increasing their internal power supply voltage. This is typically done to accelerate failures. Devices that set the internal voltage equal to an external voltage (the power supply voltage as applied to the integrated circuit power supply pin, for example) simply raise the external voltage to test for reliability. Raising the internal voltage is referred to as "stress" mode. Stress mode generally connotes the use of an artificially high VCC level.
Some integrated circuits, such as high density memories, operate on a internal operating voltage less than the external voltage VCC, which is typically 5 V. These circuits use this lower internal voltage for better reliability and lower power consumption. However, 5 V is the accepted, industry-wide value of VCC for many applications, thus requiring the use of "voltage down" converters ("VDC") integrated on chips designed to operate on a lower power supply voltage. A VDC provides a lower voltage output than the VCC external it receives.
The ideal characteristics of an on-chip voltage down converter can be seen in FIG. 1. A line 10 represents the relationship between an internal voltage VCC (VCCINT) and an external voltage VCC (VCCEXT) up to a voltage X of VCCEXT. The slope of this line is 1 so that VCCINT=VCCEXT over the range of 0 volts to voltage X. Beyond voltage X, VCCINT is constant (as shown by line 12) regardless of the voltage of VCCEXT (VCCEXT .gtoreq.X).
However, where a voltage-down converter is used for maintaining a constant VCCINT while VCCEXT varies (above voltage X), it is impossible to perform accelerated reliability testing (stress mode) because VCCINT cannot be driven above the constant level 12 by simply raising VCCEXT.
There are several ways to overcome this problem. Stress mode circuitry can be implemented to cause VCCINT to be generated equal to: (a) VCCEXT; (b) a proportion of VCCEXT; or (c) a constant voltage drop below VCCEXT. However, some stress mode circuitry uses logic gates requiring timing signals to select the test mode. The disadvantage of this approach is that the circuitry may become active accidentally. For example, during power-up of the chip, the timing signals necessary to enable the stress mode may accidentally be provided. Thus, the chip will be operating in stress mode, without the user's awareness. The chip will quickly become unreliable because of the high voltage applied to the circuit.
A prior art stress mode circuit 13 is shown schematically within FIG. 2. Circuit 13 is comprised of a stress mode circuit 13a and a VDC circuit 13b. The stress mode circuit includes a comparator 14 and transistors 16, 18, 20, 22, and 26. The VDC of circuit 13 includes transistors 28, 30, 32, 34, 36, 38 and 40. The circuit as shown has inputs coupled to receive an external supply voltage VCCEXT, a reference voltage VR, a voltage VG which is proportionate to VR, and VCCEXT/5. VG is generated as a comparison voltage to VCCEXT/5. Circuit 13 outputs VCCINT.
When VG.gtoreq.VCCEXT/5, circuit 13 is not in the stress mode. Comparator 14 outputs a high signal to a p-channel transistor 16, maintaining transistor 16 off. Transistors 18, 20 and 22 are configured as a voltage divider circuit. The voltage at a node 24 is 1/3 VCCEXT when transistor 16 is on, and is between OV and VTP (approximately 0.7 V) when transistor 16 is off.
Continuing in the case where VG&gt;VCCEXT/5, transistor 16 is off. The voltage at node 24 is low. Since node 24 is coupled to the gate of an n-channel transistor 26, transistor 26 is off or nearly off. The input to the gate electrode of transistor 28 is VR. Transistors 28, 30, 32, 34, 36, 38 and 40 are configured so that the internal voltage VCCINT supplied at a node 42 is 2VR. Transistors 38 and 40 are configured as another voltage divider circuit. The voltage at a node 44 is VCCINT/2 or VR.
Turning to the stress mode, i.e. when VCCEXT/5&gt;VG, comparator 14 outputs a low signal to turn on transistor 16. The voltage at node 24 will be 1/3 VCCEXT, which is supplied to and turns on transistor 26. The internal voltage VCCINT at node 42 will not be 2/3 VCCEXT because VR is still being applied to transistor 28. Transistors 26 and 28 are both on, which provide more current drive capability than if only transistor 26 were on. This pulls a voltage at a node 27 down more than if only transistor 26 were on. The lower voltage at node 27 will turn transistor 36 on harder. Therefore, the voltage at node 44 supplied to gate transistor 30 will be greater than 1/3 VCCEXT to compensate for VR being applied to transistor 28 during stress mode. Thus, VCCINT, which is two times the voltage at node 44, will be greater than 2/3 VCCEXT.
One of the disadvantages of this circuit when in test mode is it does not supply a VCCINT proportional to VCCEXT. Further, both VR and the voltage supplied from node 24 to the gate of transistor 26 are inputs that influence VCCINT. It is harder to tune the FIG. 2 circuit to produce a proportion of VCCEXT because the two input voltages must each be individually adjusted.
Therefore, it is a general object of the present invention to overcome the above-mentioned problems.
Another object of the present invention is to provide a circuit where the transition point for VCCINT from a constant to a ratio of VCCEXT can be set independent from that ratio.